In modern high speed computer and communication package design, the wiring between electronic circuits must adhere to strict electrical, timing and noise constraints in order for the design to function reliably to specification. Practitioners of the art will readily appreciate that many fundamental concepts of how these constraints are defined and applied vary substantially by package level. It will be demonstrated that this variation is only coincidental to the package level, and is in reality based on the correlation between the driver rise time, wiring propagation delay, and system noise characteristics. In the case of a computer chip design, line lengths are relatively short with respect to the system cycle time and the driver rise time. This makes it possible to make a critically simplifying approximation of capacitance loading. One can thus constrain net capacitance, and use this constrained capacitance value to easily determine time delay characteristics and, thus, system timing. For other types of packages, particularly, for those having longer line lengths, such as modules, cards, board, frame cables, and the like, most of the line lengths are normally far too long to be considered as a simple capacitance loads. Furthermore, timing and electrical net properties must also be taken into account by performing transmission line analysis.
A rule of thumb for determining if and when the concept of capacitive equivalence simplification can be applied is that when the propagation delay time (i.e., the time of flight) of the wire, namely, how fast electrons speed down the wire, is less then one-eighth the driver rise time of the electrical circuit for a given wire length, then the wire can be capacitively modeled. The maximum wire length for which a capacitive model can be used is given by the following equation: EQU Max length=1/8*driver.sub.-- rise.sub.-- time*wire.sub.-- time.sub.-- of.sub.-- flight,
wherein the units are:
[length]=constant*[time]*[length]/[time]
The argument made herein is that the method of the present invention does not gravitate around a well defined concept that merely extends from a chip to a higher level package. In fact, if those other packages had wire lengths sufficiently short to apply the concept of capacitive approximation, then there would be no need for the present invention. Furthermore, as chips become large enough that some or all of their nets can no longer be capacitively modeled, then the present invention applies to chips as well. Furthermore, as faster circuits are developed, driver rise times will correspondingly decrease, further reducing wire lengths. Similarly, as `faster` wires (e.g., cryogenic wires) are developed, the time of flight will likewise decrease, thus reducing the maximum wire length for the application of capacitive equivalence modeling.
In the model of the present invention, electrical constraints are typically specified by an electrical design engineer and are developed based on the system timing considerations and reliability requirements, without using the concept of lump capacitive modeling. These constraints are developed for use in applications based on the presence of various types of drivers, receivers, terminators, I/O connectors, and combinations thereof, as well as different interconnection configurations. In typical cases, as many as 1000 different unique constraint types may exist just on a chip, and many more, on higher level packages.
An electrical interconnection analysis not only involves careful evaluation of the all interconnected chip circuit technologies for compatible switching levels and function, but it must consider the effects of transmission line loading on the circuits. The fast edge switching rates of circuits require extensive analysis for accurate propagation delay prediction between circuits. This analysis that controls the inner connection delay involves meeting the design electrical noise margins in terms of chip I/O and package wiring contributions of signal reflections, edge rounding, undershoot, overshoot, incident switching and settling times. These requirements are compounded by the need to develop systems at the least expense. In prior art systems, many more book types (i.e., predefined macros that reside in a technology library and which are available by designers to be used as building blocks) exist for maximum system design optimization without incurring in the overly high cost associated with the system development.
The analysis of the interconnection networks found in real hardware designs requires extensive analysis, in addition to a substantial amount of engineering judgment. Thus, from a computational point of view, it is cost prohibitive to perform real time detailed net design analysis during the package design process. It is also logistically impossible to draw upon the required engineering judgement during the package design process, which is mostly automated. The only exception is for designs with such large design margins that the computational complexity, and correspondingly, the accuracy requirements are, correspondingly, very low.
A different methodology is required for complex designs which characteristically have small design margins, to practically insure valid designs, including the required engineering judgment, without impacting the processing time. In this latter case, the use of wiring rules may advantageously be chosen, particularly since rules are developed to define valid networks in the design, to drive the wire router in interconnecting circuits, and to check the design as a design release criteria. These wiring rules historically translate engineering electrical specifications into specific entities, such as book types, node capacitance, impedance loading, minimum or maximum length restrictions, and net topology.
Net topology defines how nodes in a network are to be interconnected. Often, the topology is defined as a daisy-chain, which links each node of the net one after another. Another type of topology includes cluster nets having a common node fanning out to other nodes of the net. Electrically, the timing or propagation delay characteristics of these two net types differ from one another. Oftentimes, nets are defined as combinations of the two, with very rigid length and book type specifications at each node.
Historically, complex net types have been defined and modeled that were so multifarious that they could not be automatically routed (by an automatic tool) within the definition of the intricate constraints set out for them. These complex net types could include one or more cluster points, either at a pin, or at some internal arbitrary position within the chip, (i.e., not at any predefined node or via point), or required at some internal within the chip or package. Those nets generally contained constraints for load balancing between branching segments for length, and/or capacitance. The result was that most of these nets, often hundreds in a given design, which could not be ordered legally, were left as overflows, and subsequently had to be manually imbedded. This manual imbedding was a lengthy and tedious process highly prone to errors, and costly to correct when found later on in the development process.
Some of the above mentioned problems and proposed solutions may be found in several publications, such as in an article entitled "IBM ES/9000 Buried Engineering Change Modeling for Verification", by C. Selinger and C. Vakirtzis, IEEE Multi-Chip Module Conference, Santa Cruz, Calif., 1992. Therein is described a method for modeling certain types of connections which could be analyzed by known analytical techniques. The process employed "mushy modeling methods" (MMM) that allows treating a T junction as a straight wire with a capacitance hanging off it. The applicability of this approach was limited to cases allowing the wiring branch to be treated as a capacitance having a tightly constrained maximum length limit, usually of the order of 8 to 10 mm. Thus, although this method was useful to, e.g., ES/9000 engineering change nets, it provided a support that used MMM, which was not very accurate, and which was restricted by the limits in length of the model that was utilized.
Much time and cost has been spent on imbedding wiring for nets which require cluster points. This is not limited to only cluster points at a pin, but, specifically, also includes cluster points that are placed at any arbitrary point in space, even those not found at a pre-existing via site. The challenge here is to provide full undiminished electrical verification, noise immunity and timing analysis with no degradation in accuracy. Current state of the art tools do not support the concept of adding constrained cluster point(s) based on transmission line characteristics. The lack of a process or methodology to address this shortcoming of previous knowledge can be costly. One of the reasons why this requirement could not be supported previously is because the logic design does not include a representation of the cluster node in the net list. Therefore, adding cluster nodes had been done manually. Additionally, critical requirements were placed on each of the fan-out wiring lengths to or from the cluster points, which required manual implementation. Since all of the work had to be done manually, it was human error prone, and the cost of finding and fixing these errors was substantial. Furthermore, if the net needed an engineering change, it likewise had to be performed fully manually, since this not was not initially automatically wired.
The present invention provides a method for adding a cluster point or points to any nets in the design of a net type where allowed. The wiring rules usage is expanded to define the added cluster node, and the design is annotated with its position logically in the net topology. Constraints are added for use in routing the net as well as constraints imposed for electrical or timing requirements/limits in the network. This facilitates the ability to legally route all of the wires of this type without overflows, which was not possible previously. Nets of this type, with added cluster points at arbitrary positions can now be imbedded fully automatically. Additionally, the resulting process is well controlled by the specification of the detailed wiring rule, repeatable by applying the same or modified wiring rule to the same or another chip or package, efficient by allowing the router to imbed all wires and verifiable by wiring rule checking methods after wiring.
Prior art solutions to the aforementioned problem have the disadvantage in that they typically support only the shortest of all the nets, since existing concepts require a capacitive lumping of nets or a completely manual process. Furthermore, it is well known in the art that long segments exhibit transmission line characteristics. These segments cannot be capacitively modeled. Transmission line nets must consider reflections and nodal impedance changes, termination reflections, induced signals from surrounding nets, effects of multiple driver switching in a given time slice, and other numerous considerations that cannot be easily or accurately approximated with the capacitance approximation methods that are known today.